Daniel Petreus

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Daniel Petreus

Locality:: 500173 Brasov, Romania
Job:: Senior ASIC/FPGA Design Engineer
Organizations:: IEEE
Education:: The University Polytechnic of Bucharest, Engineering in Foreign Language Faculty (Master of Bussiness Administration, MBA), The University Polytechnic of Bucharest (Automatic Control and Computer Science Faculty, Dipl. Engineer, BEng), Theoretical College “Grigore Moisil” (IT, Bachelor o.d.)
Status:: Freelancer
Language:: English
Experience:: ASILCOR TECHNOLOGIES SRL (Senior ASIC/FPGA/RTL Design Engineer), ASILCOR TECHNOLOGIES SRL (Senior ASIC/FPGA/RTL Design Engineer), ST-ERICSSON, (Senior ASIC/FPGA design engineer), ERICSSON, (Senior ASIC/FPGA design engineer), Duolog Technologies Ltd., (Senior ASIC/FPGA design engineer and 802.11 a/b/g/e/i/n MAC HW architect), NoBug Consulti...
Wants:: ASIC, FPGA, RTL, VHDL, Verilog, design, verification, Synthesis, STA, SoC, AMBA, ARM, Altera, Xilinx, telecommunication, wireless, etc ...
Haves:: ASIC, FPGA, RTL, VHDL, Verilog, design, verification, Synthesis, STA, SoC, AMBA, ARM, Altera, Xilinx, telecommunication, wireless, etc ...
Interests:: ASIC, FPGA, RTL, VHDL, Verilog, design, verification, Synthesis, STA, SoC, AMBA, ARM, Altera, Xilinx, telecommunication, wireless, etc ...

Daniel Petreus

Locality:: Romania
Summary:: BSS system X-Unix Alcatel-Lucent Equipment
Experience:: Deltatel Romania (Privately Held; Telecommunications industry): BSS system X-Unix, (October 2007-Present) ORANGE ROMANIA Project context: Supervise as PM the Move OMC-R network in other location. Move of IP network, X25 network (routers) ORANGE ROMANIA Project context: Change al...